The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip packaging techniques have been developed. One of these techniques is referred to as controlled collapse chip connection or "flip-chip" packaging. With packaging technology, bonding pads of the die include metal (solder) bumps. Electrical connection to the package is made when the die is "flipped" over and soldered to the package. Each bump connects to a corresponding package inner lead. The resulting packages are low profile and have low electrical resistance and a short electrical path. The output terminals of the package, which are sometimes ball-shaped conductive bump contacts, are typically disposed in a rectangular array. These packages are occasionally referred to as "Ball Grid Array" (BGA) packages. Alternatively, the output terminals of the package may be pins and such packages are commonly known as pin grid array (PGA) packages.
Once the die is attached to such a package the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially-grown silicon layer on a single crystal silicon wafer from which the die is singulated. The side of the die including the epitaxial layer and containing the transistors and other circuitry is often referred to as the circuit side or front side of the die. The circuit side of the die is positioned very near the package and opposes the back side of the die. Between the back side and the circuit side of the die is bulk silicon.
The positioning of the circuit side near the package provides many of the advantages of the flip chip. However, orienting the die with the circuit side face down on a substrate is disadvantageous in some instances. Due to this orientation of the die, the transistors and circuitry near the circuit side are not directly accessible for testing, modification or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
One particular type of semiconductor device that requires or at least benefits from accessing circuitry is a device having buried insulator (BIN) structure. Semiconductor dies including silicon-on-insulator (SOI) structure have such a BIN layer. SOI is created by forming an insulator, such as an oxide, over bulk silicon and then forming a thin layer of silicon on top of the insulator. After the silicon is formed over the insulator, circuitry is formed in the thin layer of silicon. The resulting SOI structure exhibits benefits including reduced switch capacitance, which leads to faster operation.
Techniques have been developed to access the circuitry even though it is buried under the bulk silicon. For example, near-infrared (nIR) microscopy is capable of imaging the circuitry because silicon is relatively transparent in these wavelengths of the radiation. However, because of the absorption losses of nIR radiation in silicon, it is generally required to thin the die to less than 100 microns in order to view the circuitry using nIR microscopy. For a die that is 725 microns thick, at least 625 microns of silicon is removed before nIR microscopy can be used.
Thinning the die for analysis of a flip chip bonded IC is usually accomplished by first globally thinning, wherein the silicon is thinned across the entire die surface. The silicon is globally thinned to allow viewing of the circuitry from the back side of the die using nIR microscopy. Mechanical polishing and chemical-mechanical polishing are two example methods for global thinning. Using nIR microscopy, an area is identified for accessing a particular area of the circuitry.
Once an area is identified as an area of interest and it is determined that access is needed to a particular area of the circuitry, local thinning techniques can be used to thin an area smaller than the die size. One method of local thinning, referred to as Laser microchemical etching, is typically accomplished by focusing a laser beam on the back side of the silicon surface to cause local melting of silicon in the presence of chlorine gas. The molten silicon reacts very rapidly with chlorine and forms silicon tetrachloride gas, which leaves the molten (reaction) zone.
During failure analysis or for design debug of a flip chip die having SOI structure, accessing circuitry generally involves removing substrate from the back side of the die to access a node, or milling to the node and subsequently depositing a metal on the node. Often, global and local thinning processes as described above are used to accomplish such substrate removal. Accurate control of the substrate removal process, however, is not readily achieved. The global and local thinning processes described above often involve abrasive or otherwise damaging methods. When not controlled properly, removing substrate from the back side of a flip chip die can result in damage to or destruction of circuitry and other substrate in the device. In addition, the milling process can be time-consuming, difficult to control, and expensive.
The need for a method for removing silicon is not eliminated by an approach where the back side is thinned to a distance away from the package to which the die is attached. Various part tolerances do not allow for such a simple solution to approaching the circuit side of the die from the back side of the die. One tolerance issue revolves around keeping the height of solder ball contacts on the die substantially uniform for every packaged device of a particular type. Even though the solder ball contacts have a tolerance requirement, when the solder is reflowed to attach the die to a package, the amount of change in height due to solder reflow can vary by several microns. The thickness of the die between the circuit side and back side is also subject to tolerance differences. Since the thickness of the starting silicon wafer is a non-essential parameter for making a functioning die, the die thickness is typically not accurately controlled and therefore not known.
Existing methods and systems for analyzing semiconductor chips having SOI structure would benefit from a method and/or system that makes possible such analysis without damaging the chip and while doing so in a cost-effective and efficient manner.